In the formation of integrated circuits, Shallow Trench Isolation (STI) regions are used in semiconductor wafers to define active regions. Integrated circuit devices such as transistors may then be formed at the surfaces of the active regions.
In the existing STI formation processes, the STI regions are formed by forming trenches in a silicon substrate first. The formation of the trenches includes forming a pad oxide layer over the silicon substrate, and forming a silicon nitride layer over the pad oxide layer. The silicon nitride layer, the pad oxide layer, and the silicon substrate are then etched to form the trenches. The trenches are filled with a dielectric material. A Chemical Mechanical Polish (CMP) is then performed to remove excess dielectric material that is over the silicon nitride layer. The portions of the dielectric material left in the silicon substrate thus form STI regions. The portions of the silicon substrate between the STI regions are the active regions. The remaining silicon nitride layer and the pad oxide layer are then removed. It has been found that in certain processes, such as in double-patterning processes, the thicknesses of the STI regions are not uniform. Large STI regions and small STI regions may have a significant difference in thicknesses.